Array processor

CPU Design under verification(DUV) is reconfigurable array processor which has 32 ALUs in a unit. It also has RISC microcontrollers which control the configurability, and innumerable combinations of them both is required. Verification environment is well constructed based on VMM using constrained random verification and coverage based verification. We also improve the efficiency by constructing the grid environments to reduce the verification time.

Flat panel TV

TV In recent years timing controllers have become more complicated by a variety of factors such as blocks for timing adjustment, scalability and image-processing blocks for presenting the panel's feature. In performing verification of high-definition digital TV / displays including 4K TVs, which require enormous amount of data, it is essential to carefully choose the timing, goals and methods of simulation, emulation and FPGA prototyping in the verification process. We develop the most efficient verification plans, propose / develop verification IP of image I/O, and design / verify image processing blocks.


プリンタ The system has dozens of masters (multi-CPUs) and slaves, while several bus protocols are connected to memory controller through system bus. The two of the vital points in the process of verification of such component are bus arbitration and covering communications of each master/slave. To increase verification efficiency, we fully utilize constrained random verification and functional coverage. Also using in-house bus VIP for more rigorous performance verification enables reducing time required for verification.


DSC Similar to flat panel TV, DSC/camcoder have large number of pixels. Besides, noise reduction on input data from sensor as well as image processing such as scaling have become more complicated. Furthermore, multiple formats supported CODECs, multiple MPUs, a variety of peripherals including high-speed I/Os, and system-bus memory controllers which handle heavier traffic exsist as main blocks. We are ready to offer services from designing various image processing to developing optimal verification environment.

Verification environment for Array processor

Verification environment is well constructed based on VMM using constrained random verification and coverage based verification.
Special features in this verification environment are:
to generate max 72M instructions, to generate internal bus traffic,
to realize error injection by CRV
automatic data checking by scoreboard,
to realize incremental verification environment and
to make proprietary debug environment with effective messages.

Array processor


Design under verification(DUV) is interconnect in SoC to which over 20 IPs including multiple CPUs are connected. Verification environment generates bus traffic close to actual application environment to verify several blocks including bridges, arbiters and memory controller.


Reduce simulation time by grid engine

We always face on problems that it takes some amount of time for simulation. We have constructed grid environment using 3 SUN workstations to improve this situation. We have succeeded in reducing simulation time from 17 hours to only 30 minutes under this environment.

■Grid verification environment
Grid verification environment
■Simulation time under grid computing
Grid verification environment