Services(Technology overview)

Verification Environment

Larger-scale and higher-performance LSI devices involve increasingly complex verification procedures. Today, time required for verification is said to be more than 70 % of the total development time, explaining the existing verification technologies have already reached their limit. The improvement of verification quality can no longer be expected through time consuming traditional verification methodology such as the following;

  • Prepares a large amount of test vectors with a large amount of manpower
  • Determines validity of verification requirements by "the seat of the pants" operations
  • Confirms operation by visual checks
  • Difficult-to-reuse verification environment

It should be essential to build the verification environment which is compatible with large-scale and high-performance LSI, employing a new verification methodology.

  • Generates a large amount of test patterns automatically
  • Determines achievement level of verification requirements quantitatively
  • Self-checking structures
  • Easy-to-reuse verification environment

Verification Services

Industry-standard Technologies

Verifore Verification Environment integrates

based on the following industry-standard technologies

Verification Services

Layered testbench

Easy-to-reuse verification environment

Testbench architectures are composed of 5 abstraction layers from signal layer to test layer.

Test cases can be prepared without completion of the entire verification environment, depending on the progress of lower layer design, which helps to carry out efficient verification operations.

The layered testbench design makes functions of each layer more specific, which contributes to the improvement of code reusability of each layer. For verification of SoC having similar bus structures, inter-project reuse of layers is applicable by reusing signal and command layers and by absorbing functional differences in functional layer.

Verification Services

Constrained random verification

Automatic generation and self-checking of large-volume test patterns.

The constraint-random verification increases reliability by securing tests in quantities as well as detecting bugs in corner cases, which has been difficult to find out using existing methodologies.

Directed test
  • Described state (A) is verified
  • Undescribed state (B) is not verified
  • Biased test patterns may be generated
Constrained random verification
  • Eliminates logically impossible states by constraints, i.e., not all of the states are connected
  • Accessible to state (B) which has not been thought of
  • Eliminates biased test patterns

Verification Services

Coverage based verification

Determines achievement level of verification requirements quantitatively

What functions to be verified is determined based on each verification plan. Efficient verification operation can be achieved by gaining a better understanding of which part of functions to be verified intensively and whether there is any overlapped verification item or not.

Verification Services

Assertion based verification

Increasing observability-detects functional errors which are reported near in space and time.

Identifying location of violations makes fixing bugs easier. By describing rules as assertions, specifications can also be clarified. In addition, design-dependent operational coverage can be figured out.