Services & Case Studies

Since our establishment in 2007, we have successfully led numerous hardware design and verification projects to completion. In recent years, our business has expanded to encompass large-scale projects in AI, HPC (High-Performance Computing), and autonomous driving, where we have continued to deliver proven results.

Additionally, we have built strong, long-standing relationships with major OEMs, and in recent years, we have seen a growing number of requests from semiconductor manufacturers. This is a testament to the trust and confidence we have earned by consistently providing on-time, on-budget, and high-quality verification services.

Contents

Functional Verification

We offer comprehensive verification solutions to ensure the reliability and performance of complex designs.

  • Verification Startegy
  • Verification Planning
  • Verification Environment Proposal & Development
  • Performance Verification
  • Verification IP Development
  • Verification Acceleration Using Proprietary Tools
  • Prototype Validation
  • UI/GUI Development
Technologies
  • SystemVerilog
  • UVM
  • Constrained-random verification
  • Coverage-driven verification
  • Directed verification
  • Constrained-direct verification
  • Formal verification
  • Simulator / Emulator
Design Domains
  • AI
  • Processors(RISC-V, ARM)
  • High-Performancce Computing
  • Autonomous driving
  • Image processing
  • Interconnect
  • Memory controller

Innovative Products Engineered In-House

Solutions

Our proprietary solutions are designed to accelerate and enhance the verification process, leveraging our in-house development expertise.

  • Verification Accelerators
    • Verification accelerators utilizing general-purpose FPGA boardsタ
    • Test Pattern Generators:
      • Mathematical approaches
      • Minimum test generation to achieve 100% coverage
  • Proprietary Verification IPs
    • AMBA(APB/AHB/AXI)
    • Processor Bus Interfaces
    • MEMC
    • Pixel Input/Output

Case Studies & Success Stories

Enhancing verification efficiency through constrained random testing and coverage-driven methodologies

Hierarchical Verification Environment for RISC-V Based IP

  • Project Overview:
    • Developed a hierarchical verification environment focused on reusability and portability for a suite of RISC-V based IPs.
  • Challenges:
    • The goal was to enable scenario generation in higher-level languages such as Python and C, while ensuring
      those scenarios could run independently of the underlying verification environment or simulation platform.
  • Solution Implemented:
    • Designed and implemented a flexible, hierarchical verification environment
    • Enabled test scenario description using Python and C
    • Leveraged iTGV to automatically generate minimal yet effective test suites
  • Results:
    • Successfully completed the development of the initial verification infrastructure
    • Conducted dry-run tests targeting the real system without issues, confirming the effectiveness of the approach

RTL Verification of a High-Performance Scalable Array Processor

  • Project Overview:
    • RTL verification of a configurable and scalable array processor featuring 32 execution units (EUs) per processing unit.
  • Challenges:
    • Even in its minimum configuration, the processor integrated 32 EUs per unit and included a RISC processor
      to control each unit. The sheer number of possible instruction combinations resulted in a verification space
      of astronomical scale. The challenge was to efficiently verify the functionality under limited engineering
      and compute resources.
  • Solution Implemented:
    • Accelerated simulation using a distributed grid computing environment
    • Coverage-driven verification based on UVM with constrained random testing to ensure comprehensive
      functional coverage and identify corner cases
    • Developed and utilized custom in-house Verification IP (VIP) for streamlined verification setup
  • Results:
    • Successfully completed verification within 6 months with a team of only 2 engineers
    • Discovered over 10 critical bugs, ensuring reliable functionality of the target IP
    • Achieved high-quality RTL verification under resource-constrained conditions

Functional Verification of Custom RISC-V Extension Instructions

  • Project Overview:
    • Functional Verification of Custom RISC-V Extension Instructions
  • Challenges:
    • Ensuring correct behavior of each extension instruction, particularly
      under pipeline hazards and other complex execution conditions.
  • Solution Implemented:
    • Automatically generated test patterns using iTGV to trigger pipeline hazards
    • Converted test patterns into RISC-V assembly code for execution
    • Built a simulation environment using SystemVerilog
  • Results:
    • Verified functional correctness of all custom extension instructions
    • Confirmed no adverse impact on the processor's baseline functionality

Functional and Performance Verification of Interconnect

  • Project Overview:
    • Verification of an interconnect system where dozens of MPUs access shared memory via a common bus.
  • Challenges:
    • Developed master models for all MPUs and memory models,
      along with custom performance monitors to measure bus efficiency and latency.
  • Solution Implemented:
    • Created a simulation environment using SystemVerilog and UVM.
    • Developed performance monitoring modules to analyze data flow and bottlenecks.
  • Results:
    • Achieved bug-free operation of the interconnect under all test scenarios.
    • Identified key areas for improvement and design considerations for next-generation bus development.

Design & Verification of Image Processing IP Blocks

  • Project Overview:
    • Specification, RTL design, and verification of multiple functional blocks for high-resolution image processing (4K / 8K).
  • Challenges:
    • Efficient processing of massive image data involving functions such as image composition, scaling, and output splitting,
      all within strict simulation time constraints.
  • Solution Implemented:
    • Accelerated verification through a hybrid simulation and emulation approach.
    • Applied proprietary know-how to minimize simulation time for large data volumes.
  • Results:
    • Achieved bug-free operation across all assigned blocks (verified using pre-production silicon evaluation).
    • Completed the verification phase on schedule.
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