The processor under verification was a configurable array processor with 32 execution units per unit. Additionally, a RISC microcontroller was responsible for managing its configurability.
The sheer number of possible instruction combinations alone resulted in an astronomically large test space.
To efficiently cover this vast combination space, Verifore adopted a constrained random verification approach, making it the core of the verification environment.
At the time, the Verification Methodology Manual (VMM) was still relatively unknown, but we fully embraced it to enhance verification efficiency. Furthermore, to accelerate the process, we implemented a grid computing environment, significantly boosting performance.
As a result, with just two verification engineers, we successfully completed the entire verification process in an impressive six months.

Modern timing controllers have become increasingly complex, incorporating not only traditional timing adjustment blocks and scalability features but also numerous image processing blocks designed to enhance panel characteristics.
When targeting high-resolution panels such as 4K and 8K, the sheer volume of data presents significant challenges.
This makes it crucial to determine which verification methods—simulation, emulation, or FPGA prototyping—should be used at each stage of the verification process and for what specific purposes.
By implementing a well-structured, comprehensive verification strategy, we successfully completed the verification process on schedule, as planned.

The system architecture consisted of dozens of masters (including multi-CPU configurations) and slaves, with multiple bus protocols connecting to the memory controller via a system bus.
In such a setup, the key verification challenges were ensuring proper bus arbitration and achieving comprehensive coverage of master-slave communication across the system.
To maximize verification efficiency, we leveraged constrained random testing and functional coverage, ensuring a systematic approach to test all critical scenarios. Additionally, to conduct rigorous performance verification, we utilized our proprietary bus verification IP (VIP).
This strategy allowed us to complete the verification process within a relatively short timeframe, ensuring the system met all functional and performance requirements.

As with TVs, digital still cameras (DSCs) must process an enormous number of pixels, making image processing increasingly complex.
This includes noise reduction, scaling, and other enhancements applied to sensor input images. Additionally, DSC systems integrate multi-format CODECs, multiple MPUs, various peripherals (including high-speed I/O), and system buses/memory controllers managing heavy traffic loads as core components.
At Verifore, we provide end-to-end solutions, from image processing design to the development of optimized verification environments, ensuring high efficiency and performance in DSC systems.

The verification target was the entire interconnect subsystem within an SoC, where dozens of IP cores, including CPUs, were interconnected.
The objective was to validate the system’s behavior under real-world traffic conditions, covering various bridges, arbiters (including protocol verification), and the DRAM controller.
For this project, we implemented a UVM-based SystemVerilog verification methodology, leveraging both constrained random verification and directed testing.
Key features of our approach included:
- Traffic generation using constrained random verification
- Automated data checking via a scoreboard
- Bus protocol validation using bus monitors and assertions
- Functional coverage collection and statistical performance analysis
- A hierarchical verification environment enabling easy creation of directed test cases
Thanks to this structured and efficient methodology, we successfully completed the verification on time.